1. Field of the Invention
The present invention relates to reaction chambers used for the deposition of material layers during fabrication of semiconductor devices. Specifically, the present invention relates to an improved gas delivery device for improved control of chemical vapor delivery within a semiconductor device fabrication chamber.
2. State of the Art
As is well known, processes for semiconductor device fabrication generally involve the deposition and processing of one or more material layers on a semiconductor substrate. Often, these different material layers are formed using well-known chemical vapor deposition (CVD) processes, such as thermally enhanced (TE) CVD, plasma enhanced (PE) CVD or high density plasma (HDP) CVD. Such techniques require placing a semiconductor substrate within a sealed reaction chamber and introducing one or more chemical vapors into the sealed reaction chamber under conditions known to result in the deposition of a desired material. However, in order to ensure the deposition of high-quality material layers using known deposition techniques, the quantity and quality of the gaseous chemicals entering the sealed reaction chamber must be carefully controlled throughout the deposition process. Failure to control the amount of chemical vapor entering a reaction chamber, the distribution of chemical vapor within the reaction chamber, or the rate at which a given amount of chemical vapor enters the reaction chamber can each result in low-quality material layers that substantially compromise the quality of the subsequently completed semiconductor device.
For example, HDP CVD processes are often used to fill various features, such as isolation gaps or trenches, included in an intermediate semiconductor device structure with a dielectric material, such as silicon dioxide (SiO2). HDP CVD processes are currently favored for filling isolation gaps or trenches because the simultaneous dielectric deposition and sputter etch produced by such processes allows small, high aspect ratio features to be reliably filled with dielectric material. However, imprecise control of the reactant gases used for HDP deposition will either result in damage to underlying device features or deposition of a low-quality dielectric layer, either of which significantly reduces the performance and reliability of subsequently completed semiconductor devices.
Presently used HDP CVD processes often utilize a gas mixture containing oxygen (O2), silane (SiH4), and inert gases, such as argon (Ar), in combination with plasma generation and application of an RF bias to the target substrate, to achieve simultaneous dielectric deposition and sputter etching. The interaction of SiH4 and O2 molecules in the HDP environment results in the deposition of silicon dioxide (SiO2) over the semiconductor substrate. However, as SiO2 is deposited over the semiconductor substrate, molecules of the inert gas included in the gas mixture are ionized by the plasma produced within the chamber. Due to the RF bias applied to the semiconductor substrate, the ionized molecules accelerate toward and impinge upon the surface of the substrate. As a result, SiO2 is simultaneously deposited on the wafer surface and sputter etched by accelerated ionized particles. In most HDP CVD processes, the ratio of deposition rate to etch rate ranges from about 2% to about 20%. It is the simultaneous deposition and sputter etch created by HDP CVD processes that allow higher aspect ratio features to be filled with the desired dielectric material.
In order to better describe the simultaneous deposition and sputter etch of a typical HDP CVD process, drawing FIG. 1 through FIG. 4 schematically illustrate various stages of such a process. Illustrated in drawing FIG. 1 is an intermediate semiconductor device 5 including a semiconductor substrate 10 with an isolation gap 12 disposed between two circuit elements 14. As can be seen in drawing FIG. 1, due to the interaction of SiH4 with O2 during a typical HDP CVD process, a layer of SiO2 16 begins to form over the two circuit elements 14 and within the isolation gap 12. As the SiO2 16 is deposited, however, charged ions (not shown in drawing FIG. 1) impinge on and sputter etch the newly deposited layer of SiO2 16. Because the sputter etch rate created by the impinging ions is approximately three to four times higher at 45° than it is at 90°, facets 20 form at the corners of the circuit elements 14 during the deposition process. Illustrated in drawing FIGS. 2 through 4 is the continuing growth of the layer of SiO2 16 and filling of the isolation gap 12 as would be expected from an HDP process having an optimized deposition-to-etch ratio.
However, as is well known, the deposition-to-etch ratio can be controlled by varying the rate of flow of SiH4 or other process gases into the reaction chamber. For example, if the flow rate of SiH4 is increased, the deposition rate of the HDP CVD process will increase. As shown in drawing FIG. 5, if the deposition-to-etch ratio is increased above the optimum, the facets 20 begin moving away from the corners of circuit elements 14, and cusps 22 begin to form on sidewalls 24 of the isolation gap 12. Cusp formation is believed to result from redeposition of etched SiO2 on opposing surfaces through line-of-sight redeposition. Significantly, the rate of redeposition increases as the distance (represented by the letter “D”) between opposing facets 20 decreases. As the facets 20 move away from the corners of the circuit elements 14, the line-of-sight paths are shortened and sidewall redeposition is increased. Eventually, the cusps 22 meet, preventing further deposition below the cusps 22 and creating a void 25 in the dielectric material layer SiO2 16 deposited within the isolation gap 12, as can be seen in drawing FIG. 6.
Additionally, if the rate at which inert gas (e.g., Ar) is introduced into an HDP CVD chamber is increased or flow of SiH4 is decreased, the sputter etch rate of the HDP CVD process will increase, thereby decreasing the deposition-to-etch ratio. As shown in drawing FIG. 7, decreasing the deposition-to-etch ratio can result in the etching or “clipping” of material from the corners 23 of the circuit elements 14. Clipping progressively damages the circuit elements as the HDP CVD process progresses and will potentially compromise the performance of the circuit elements 14 or render the circuit elements 14 completely inoperable.
As is easily appreciated from the foregoing, the flow rate of reactant gases used to effect HDP CVD processes, particularly those gases that affect the deposition-to-etch ratio, must be precisely controlled. This is especially true as the device features to be filled by HDP CVD processes shrink well below 0.5 μm. However, known gas delivery systems used in conjunction with HDP CVD reactors do not provide the range of control necessary to consistently deposit high quality dielectric material within the ever-shrinking, high-aspect-ratio device features included in state of the art semiconductor devices.
A typical gas distribution device 28 used for gas delivery within an HDP CVD reaction chamber is illustrated in drawing FIG. 8. Such a gas distribution device 28 includes a single mass flow control valve (“MFC”) 30, a gas inlet 32, a manifold ring 34, and a plurality of nozzles 36a-36h. Often during an initial period of a “gas-on” phase of an HDP CVD process, a build up of process gas pressure occurs within the gas delivery system, and where a gas distribution device 28 such as the device illustrated in drawing FIG. 8 is used, the initial build up of process gas pressure results in a high initial flow of reactant gas through the nozzles located closest to the gas inlet 32. However, while this high flow is occurring at the nozzles 36a, 36h closest to the gas inlet 32, very little, if any, reactant gas flows through those nozzles 36d, 36e located farthest away from the gas inlet 32 for approximately one to two seconds. Thus, deposition of SiO2 on the target substrate begins in the area of the substrate underlying those nozzles 36a, 36h closest to the gas inlet 32 before any deposition has taken place in the area of the target substrate underlying those nozzles 36d, 36e located farthest from the gas inlet 32. Moreover, the initial build up of process gas pressure causes process gas to flow through those nozzles 36a, 36h closest to the gas inlet 32 at an undesirably high rate, and the deposition-to-etch ratio of the HDP CVD process moves away from the desired optimum, until the pressure of the process gas within the gas distribution device 28 stabilizes.
Where a gas delivery ring such as the one illustrated in drawing FIG. 8 is used to deliver SiH4 during an HDP CVD process, the quality of the resulting dielectric material may, therefore, be severely compromised. During the initial period of an SiH4 gas-on phase, the high flow of SiH4 through the nozzles 36a, 36h located closest to the gas inlet 32 of the gas distribution device 28 will cause the deposition-to-etch ratio to increase away from the desired optimum. Even though this inconsistency may last as little as one second, the deposition-to-etch ratio is effected long enough to affect deposition of at least the initial nuclear layer of the deposited dielectric material in such a way as to cause voids or other material inconsistencies within the deposited dielectric layer as the deposition process continues. Thus, the inconsistent gas flow provided by known gas delivery rings often renders entire wafers or portions of wafers unusable.
As can be easily appreciated, there is a need in the art for a gas delivery apparatus that allows reliable, precise control of gas flow at all times during a material deposition process. Such a device would not only be desirable because it would eliminate the problems caused by the inconsistent delivery of process gases associated with known devices, but such a device will likely prove necessary as the dimensions of state of the art semiconductor devices continue shrink.